March 9, 2016

Host: Ops A La Carte
Speaker: John Cooper, Senior Reliability Engineer
Time: 12:00pm-1:00pm Pacific Time
Register:
https://attendee.gotowebinar.com/register/8806845518889777665

Many of us are involved in HALT testing; sometimes we wonder if we are doing it correctly or why it is done a certain way. Some of us may not understand it and would like a basic review.

This webinar will include an introduction to HALT, an understanding of what it will do, and what it will not do, and how to plan for it. We will explore fixturing, setup, functional verification, and the actual running of the test. We will discuss the real value of HALT.

Advanced topics will be touched on such as pitfalls of HALT, how it can be misunderstood, and some case studies.

Tune in to this webinar for a refresher; invite your associates, such as design engineers or project managers, who would appreciate understanding HALT and might have questions.

To Register and for more info, please call 408.654.0499, x203

We look forward to seeing you at all of our events!

Jay and all the Ops Staff

FREE WEBINAR – February 10, 2016

Host: Ops A La Carte
Speaker: James McLinn, Senior Reliability Engineer
Time: 12:00pm-1:00pm Pacific Time
Register: gotowebinar.com

Selecting a set of stresses for accelerated life testing can be a challenge for some accelerated life tests. Determining the best set of stresses is only the start of the reliability challenge. Should one employ a combination of temperature and vibration, temperature and humidity, mechanical stress and temperature, corrosive materials and temperature, temperature cycles and vibration or some other stress combination? If one important goal of the ALT is to simulate the customer environment and thereby extrapolate the test results to the field, then selecting the best combination of stresses is important.

Not all customers have the same set of conditions in the field. Many customers experience more than two operating stresses in the field. It may be that four or more stresses may be present. Thus, selecting only two stresses will represent a compromise to field simulation. Add high levels of acceleration in each selected stress and complications arise. There may also be issues with non-linear behavior appearing in the test results.

This webinar will present approaches to selecting the best set of two stresses, showing ways to limit the test conditions and then handling some of the data analysis issues resulting from any non-linear test results. All of these considerations are important to achieving successful ALT results and then extrapolating these to the field.

January 30, 2016
Fracture Mechanics & Fatigue: Theory and Modeling for Mechanical Engineers
by Dr. Metin Ozen, ASME Fellow, Principal
Ozen Engineering Inc, Sunnyvale, CA
(co-sponsored ASME SCV Chapter)

Date: Saturday, January 30, 2016
Time: 9:00 AM – 4:00 PM
Location: Santa Clara University, CA 95054
Admission: ASME or IEEE Member: $80 per person, Non-Member: $120 per person; Student, Unemployed or Retired Member: $45 per person.

All in-person attendees will receive a light lunch. Breaks with snacks and drinks will be part of the seminar experience.

This course covers detailed information on the Fracture Mechanics and Fatigue theory as well as numerical modeling. The course reviews the fundamentals of fracture mechanics and fatigue; history, derivation of mathematical expressions for stress intensity factors; 2D versus 3D, crack tip stress field, three modes of fracture, maximum principal stress criterion, crack initiation and crack propagation, strain energy density theorem, J-Integral, mixed mode cracking, XFEM method, cohesive zone modeling, implementation of crack modeling in ANSYS Workbench, fatigue crack growth, stress/strain/energy based fatigue, numerical modeling of fatigue.

Attendees will receive instructions to download free 30 days ANSYS/Mechanical software license at the end of the seminar (restrictions apply). Attendees will not need either the software installed on their system or experience with ANSYS to attend the seminar. Software can be downloaded after the seminar to practice the workshop problems demonstrated during the course.

Register here! Please do NOT remove the promotional code ‘IEEE’ listed above the ‘Order Now’ button on the registration page.

Jaunary 25-28, 2016 in Tucson, AZ

The Annual Reliability and Maintainability Symposium (RAMS®) is the premier event in the reliability, availability, and maintainability engineering disciplines. Combining tutorials, presentations, CEUs, certifications, and networking into one week-long program, the RAMS® delivers cutting edge information to all technical industries.

We have speakers at this conference so make a point to visit their sessions. And please stop by and say ‘hi’ to us at our booth!

For more information about this Conference, visit www.rams.org

October 7, 2015

Food sponsored by
ICE Labs, ISO 9001 & 17025 Reliability Test Lab

Title: Engineering The Right Accelerated Life Tests For Reliability Qualification – Customer use conditions vs. industry standards based approaches
Invited Speaker: Sudarshan Rangaraj, Ph.D, Amazon Lab126 Reliability Manager
Time: Check in and food at 6:00PM – 6:30 PM
Presentation from 6:30 PM to 7:30 PM
Location: Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051 (Meeting will be in the cafeteria, Building B)
Admission: Open to all IEEE members and non-members for FREE!
Abstract: Various reliability testing standards like JEDEC/AED/MIL/IEC etc. are commonly used in the semi-conductor and consumer electronics for reliability qualification of IC components and consumer electronics devices. However, “blanket” qualification criteria that are not based on knowledge of customers’ usage behaviors and physics of failure expose the manufacturers to two risks. At one end of the spectrum lies the risk of over-design and added cost while on the other end lie the risks of field failures, warranty costs, negative user experience and erosion of the corporation’s brand. The present talk will draw upon examples from semi-conductor chip/package and consumer electronics to compare qualification criteria based on standards to those based upon product use conditions. Widely prevalent failure modes like moisture diffusion in polymers and fatigue of solders will be invoked to make quantitative comparisons between standards and use conditions based reliability qualification criteria. The talk will take a critical look at JEDEC criteria for temperature-humidity, thermal cycling and bake testing.

FREE WEBINAR – October 7, 2015

Host: Ops A La Carte
Speaker: Robert Mueller, Senior Reliability Engineer
Date:  October 7, 2015
Time
: 12:00pm-1:00pm Pacific Time

Root Cause Analysis of software defects continues to confirm that design defects remain the dominate root cause of software system failures. Yet, few non-regulated software development teams using ‘agile’ development methodologies emphasize formal design reviews in their processes. The design Failure Mode & Effects Analysis methodology (dFMEA) is a proven review tool for enhancing the reliability of a product’s design. Incorporating key elements of dFMEA methodology into each iteration of the ‘agile’ development process gives the product development team a continuously increasing product reliability growth profile from the very start of the software development process.

This Webinar will explore how software development teams have successfully added the elements of the dFMEA process to their Scrum (‘agile’) development processes, sprint by sprint. We will explore how teams augmented their definition of done (DoD) with FMEA process deliverables. We will explore what design artifacts (e.g., system models, object models, sequence or interaction diagrams, etc.) are typically used with the dFMEA enhanced sw design review process. We will also explore the advantages of prioritizing the product’s backlog using both an item’s value and its technical (e.g., reliability) risk.

Join us in this in-depth exploration of how FMEA can be integrated into the ‘agile’ software development process. Most of all, do not forget to bring your questions. “Yah-buts” are encouraged!

 

I’m Happy To Introduce Jon Ferguson
Our New HALT & HASS Labs® Lab Manager!

Jon has 18 plus years of reliability and quality experience, and has worked his way through the ranks from operator/assembler to Reliability Engineer at Quantum Corp. During his time at Quantum he was part of a team that developed a state of the art reliability lab and later brought his experience to Harmonic Inc., Tyco Healthcare, and Apple.

He has a history with Ops; for 4 years Jon managed the HALT & HASS Lab operations and has recently returned. He has also been managing the external lab projects and partnerships.

Jon received his training at Devry in Phoenix, AZ and later in avionics through the US Navy where he served for 6 years performing I-Level and Depot level debug on P3C Orion communication and RADAR equipment.

Jon has also co-authored 3 papers that were presented at RAMS, “Reliability Stress Test Method: Impact on the New Product Introduction Process, Time to Market, Field Reliability Impact and Reliability Assessment.” RAMS Symposium 2002; Design-evaluation and product reliability assessment using accelerated fatigue-life tests, RAMS Symposium 2000; Accelerated reliability test: Solder Defect Exposed, RAMS Symposium 1999.

FREE WEBINAR – September 2, 2015
Host: Ops A La Carte
Speaker: John Cooper, Senior Reliability Engineer and Instructor
Time: 12:00pm-1:00pm Pacific TimeWhether you are in a startup company, pressed to meet a demanding schedule, or if you are in reliability engineering and are offering services to a startup, it’s important to understand how startup companies operate, and what their needs are in regards to product reliability.

Many startups today are fast-paced, driven by young college grads, and often funded through crowdsharing. They may be sponsored by one of several well-known venture capital incubators.

One of the challenges in modern reliability engineering is to help management and engineers understand the value and process of reliability engineering. In an electronic company, there may challenges to get people to understand such tools as HALT, or FMEA. In a crowdsharing based startup, the challenge is an order of magnitude more difficult. The risk of failure is much higher, when you consider the consequences of products that fail soon after shipment.

A startup company is under pressure to meet goals such as the following:
1) Quicker: Product development time must be shorter – time to market is much more critical.
2) Products must be better – higher performance, better quality and reliability (as demonstrated by smart phones, for example).
3) Products must be lower cost, which is cost of ownership, including warranty cost.

We will examine what the special reliability needs are for startup companies, and consider what tools make more sense – tools such as HALT – for results must occur in days, not weeks. In startups, decisions are made real-time, meetings are short; there is no “long term”.

Join us in this webinar, and share your questions or concerns.

September 9-11, 2015 in Boston, MA

The 2015 Accelerated Stress Testing and Reliability (ASTR) Conference is focused on highlighting cutting-edge methods to deliver maximum cost-benefits from reliability testing. ASTR 2015 is relevant to manufacturers in the aerospace, automotive, consumer electronics, defense, medical, telecommunications and other industries where reliability is a key driver of operational and business success. If your company needs to improve product testing with a goal to improve reliability, reduce warranty costs, improve profits, gain market share, and be more competitive, then the 2015 ASTR Conference is for you!

Abstract Submission Deadline is April 17, 2015; more info here.

For more information about this Conference, visit www.ieee-astr.org

August 6, 2015

Food sponsored by
ICE Labs, ISO 9001 & 17025 Reliability Test Lab

Title: Macroscopic & Stochastic Aspects of Negative Bias Temperature Instability
Invited Speaker: Souvik Mahapatra, Professor of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India
Time: Check in and food at 6:00PM – 6:30 PM
Presentation from 6:30 PM to 7:30 PM
Location: Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051 (Meeting will be in the cafeteria) (View Map)
Admission: Open to all IEEE members and non-members for FREE!
Abstract: Negative Bias Temperature Instability (NBTI) is a crucial reliability concern for modern day state-of-the-art CMOS technologies. NBTI results in shift in MOSFET parameters, such as threshold voltage, drain current, etc., over time, and therefore causes long-time failure of CMOS integrated circuits. It is very important to understand the fundamental physical mechanism responsible for NBTI and develop suitable models to predict device and resultant circuit degradation at end product life.

In this talk, the underlying physical processes responsible for NBTI in High-K Metal Gate (HKMG) MOSFETs will be briefly reviewed. Defect generation in MOSFET gate oxide will be explained from both macroscopic and stochastic viewpoints, which will be respectively useful to explain NBTI degradation in large and small area devices. This novel simulation framework can explain DC and AC NBTI degradation under various operating conditions such as different operating voltage, temperature, frequency and duty cycle in large area devices, as well as NBTI variability in small area devices. Furthermore, a compact model will be developed to simulate NBTI induced circuit degradation using SPICE simulation, and specific example of variable NBTI impact on SRAM performance parameters, such as read and hold static noise margin and write access time will be discussed.

For more information and to register, visit: Eventbrite Registration