IEEE

March 17, 2016

Date: Thursday, March 17, 2016
Time: 8:00 AM – 45:00 PM (Breakfast & Lunch are provided)
Location: Juniper Networks (1194 North Mathilda Ave, Sunnyvale 94089. Building 1, Tuolumne Room)
Attendance: Registration is Free!! Attend on-site or Remote via WebEx

Join us on Thursday, March 17, 2016 for a day of learning, innovation and networking at the 5th Annual IEEE International Reliability Innovations Conference. The conference serves as a leading platform for engineering professionals to share innovative concepts, design, methodologies, tools and applications to address challenges in reliability. Engage in technical sessions, workshops, seminars and panel sessions on the latest advancement and network with like-minded professionals from all over the world.

The conference is brought to you by Cisco Systems, Juniper Networks and OPS Ala carte in collaboration with the IEEE Reliability Society (SCV Chapters), along with our prominent sponsors.

We look forward to seeing you at all of our events!

Jay and all the Ops Staff

October 7, 2015

Food sponsored by
ICE Labs, ISO 9001 & 17025 Reliability Test Lab

Title: Engineering The Right Accelerated Life Tests For Reliability Qualification – Customer use conditions vs. industry standards based approaches
Invited Speaker: Sudarshan Rangaraj, Ph.D, Amazon Lab126 Reliability Manager
Time: Check in and food at 6:00PM – 6:30 PM
Presentation from 6:30 PM to 7:30 PM
Location: Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051 (Meeting will be in the cafeteria, Building B)
Admission: Open to all IEEE members and non-members for FREE!
Abstract: Various reliability testing standards like JEDEC/AED/MIL/IEC etc. are commonly used in the semi-conductor and consumer electronics for reliability qualification of IC components and consumer electronics devices. However, “blanket” qualification criteria that are not based on knowledge of customers’ usage behaviors and physics of failure expose the manufacturers to two risks. At one end of the spectrum lies the risk of over-design and added cost while on the other end lie the risks of field failures, warranty costs, negative user experience and erosion of the corporation’s brand. The present talk will draw upon examples from semi-conductor chip/package and consumer electronics to compare qualification criteria based on standards to those based upon product use conditions. Widely prevalent failure modes like moisture diffusion in polymers and fatigue of solders will be invoked to make quantitative comparisons between standards and use conditions based reliability qualification criteria. The talk will take a critical look at JEDEC criteria for temperature-humidity, thermal cycling and bake testing.

August 6, 2015

Food sponsored by
ICE Labs, ISO 9001 & 17025 Reliability Test Lab

Title: Macroscopic & Stochastic Aspects of Negative Bias Temperature Instability
Invited Speaker: Souvik Mahapatra, Professor of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India
Time: Check in and food at 6:00PM – 6:30 PM
Presentation from 6:30 PM to 7:30 PM
Location: Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051 (Meeting will be in the cafeteria) (View Map)
Admission: Open to all IEEE members and non-members for FREE!
Abstract: Negative Bias Temperature Instability (NBTI) is a crucial reliability concern for modern day state-of-the-art CMOS technologies. NBTI results in shift in MOSFET parameters, such as threshold voltage, drain current, etc., over time, and therefore causes long-time failure of CMOS integrated circuits. It is very important to understand the fundamental physical mechanism responsible for NBTI and develop suitable models to predict device and resultant circuit degradation at end product life.

In this talk, the underlying physical processes responsible for NBTI in High-K Metal Gate (HKMG) MOSFETs will be briefly reviewed. Defect generation in MOSFET gate oxide will be explained from both macroscopic and stochastic viewpoints, which will be respectively useful to explain NBTI degradation in large and small area devices. This novel simulation framework can explain DC and AC NBTI degradation under various operating conditions such as different operating voltage, temperature, frequency and duty cycle in large area devices, as well as NBTI variability in small area devices. Furthermore, a compact model will be developed to simulate NBTI induced circuit degradation using SPICE simulation, and specific example of variable NBTI impact on SRAM performance parameters, such as read and hold static noise margin and write access time will be discussed.

For more information and to register, visit: Eventbrite Registration

4th Annual IEEE International Reliability Innovations Conference – March 19, 2015 in San Jose and via WebEx

Join the 4th Annual IEEE International Reliability Innovations Conference. There are wonderful learning & networking opportunities in this event. Best paper will receive an iPAD. Submission of previously unpublished work and results are highly encouraged. Published work will also be accepted at the organization committee’s discretion.

For more information, visit www.reliabilityinnovations.org