August 4, 2016
IEEE Santa Clara Valley Reliability

Chapter Meeting
Surfaces, Interfaces and Microelectronic Packaging
by Dr. Guna Selvaduray, Ph.D.

Date: Thursday, August 4, 2016
Time: 6:00pm – 8:00pm
6:00pm – 6:30pm – Check-in
6:30pm – 8:00pm – Presentation

Location: Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051 (Meeting will be in the cafeteria, Building B)
Admission: Open to all IEEE members and non-members for FREE

All in-person attendees will receive a light lunch. Breaks with snacks and drinks will be part of the seminar experience.

Abstract: Of the total cost involved in producing a microelectronic component, between 50% to 90% goes towards the packaging, depending on the specific type of die and packaging technology. However, approximately 95% of the reliability issues are actually related to the packaging rather than the die. There are a variety of surfaces and interfaces, the integrity of which needs to be maintained at all times, in order for the die to be able to function reliably over its service life. Some of these surfaces and interfaces are obvious while others are not. The integrity of these surfaces can have a major impact on the long term reliability of the packaged die. The detailed composition of the interface can also change over time. This presentation will focus on a discussion of the interfacial interactions between Pb-free solders and substrates, the nature of these interactions, the intermetallic compounds (IMC) that are formed, and how these interaction layers can change over time.

Attendance to this seminar will count towards professional development hours for IEEE, ASQ. Please feel free to forward this message to your friends and colleagues. – Register here!

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