SITUATION
Semiconductor development teams often rely too heavily on their foundries to perform all of the reliability development and testing activities. Customers must own this and must be ready to tell their foundry what they would like done (or in the case of reliability testing, they may need to perform the qualification testing themselves or at a 3rd party lab), and when they don't have the expertise in-house, we can help.

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METHODOLOGY

As with every other type of product, semiconductors require a carefully laid out reliability plan that addresses each phase of the product life cycle. When we do this, we can then integrate this process into the development process to have a very cohesive reliability program. Below, we have described the reliability life cycle process for semiconductor products.

DEVELOPMENT PHASE

BIR (Built In Reliability) during wafer fabrication process development.

1) Each vertical process module (i.e. oxide growth, plasma etch, etc. ) should have reliability metrics, measured on test structures (i.e. gate oxide capacitors, poly resistors, metal traces, etc.). This is not an issue using a wafer foundry with an established qualified process, but getting the "due diligence" information from the foundry and auditing the process is an important reliability engineering task.

2) Evaluation of the wafer process qualification results, process control results, ongoing quality/reliability monitor data.

DFR (Design For Reliability)

1) Participate in the technology vs. design development process, working with Design Engineering to ensure a reliable final product.

DFT (Design For Testability) for both volume production pass/fail testing and during HTOL (High Temp. Operating Life test) to ensure very high fault coverage and toggle rate coverage of gates (for over 90 % gate toggle coverage during dynamic burn-in).

PRODUCT QUALIFICATION/VOLUME PRODUCTION RAMPING PHASE:

1) Develop Reliability Qualification Plan.

2) Develop Highly Accelerated Lifetime Testing procedure to find weaknesses.

3) Design all required hardware for Product Reliability Qualification, i.e. dynamic lite test burn in board, Highly Accelerated Temperature/Humidity Stress Testing (HAST) board, etc.

4) Direct the Reliability Qualification process.

5) Conduct Failure Analysis of qualification test rejects, directing development of corrective action plans, close on corrective actions.

6) Develop SLBC (Statistical Bin Limit Control) procedures to remove the "outliers" from the normal distribution of product. This is a very powerful tool to enhance product reliability and reduce field failure rate.

PRODUCT MATURITY PHASE:

1) Review/direct/manage Ongoing Reliability Monitors from wafer fabrication and based on finished product reliability testing.

2) Direct Failure Analysis/corrective actions based on reliability monitor failures and customer returns.

3) Propose design changes to address field-and monitor failures.

4) Evaluate proposed fabrication process changes.

CASE STUDIES/OPTIONS
The following case studies and options provide example approaches. We shall tailor our approach to meet your specific situation.

1) Development Phase Reliability for a Custom IC
A small semiconductor company was developing a new custom chip and was using a foundry over in Asia to fabricate the chip. We helped evaluate the wafer process qualification results, process control results, and ongoing quality/reliability monitor data. Then we performed failure analysis by deprocessing/cross sectioning a sample wafers to analyze potential reliability issues.

2) Test Phase Reliability for a custom ASIC
A system company was developing a custom ASIC for their product. We came in and helped develop the qualification test plan to assure high reliability before integrating into the next higher assembly.

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